This Week's Focus: Microcontroller Watch
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Cypress Semiconductor Teams with Arm
for Secure IoT MCU Solution

Cypress Semiconductor has expanded its collaboration with Arm to provide management of IoT edge nodes. The solution integrates the Arm Pelion IoT Platform with Cypress' low power, dual-core PSoC 6 microcontrollers (MCUs) and CYW4343W Wi-Fi and Bluetooth combo radios. PSoC 6 provides Arm v7-M hardware-based security that adheres to the highest level of device protection defined by the Arm Platform Security Architecture (PSA).
Cypress and Arm demonstrated hardware-secured onboarding and communication through the integration of the dual-core PSoC 6 MCU and Pelion IoT Platform in the Arm booth at Arm TechCon last month. In the demo, the PSoC 6 was running Arm's PSA-defined Secure Partition Manager to be supported in Arm Mbed OS version 5.11 open-source embedded operating system, which will be available this December.


New CPU Core Boosts Performance 
for Renesas MCUs

Renesas Electronics has announced the development of its third-generation 32-bit RX CPU core, the RXv3. The RXv3 CPU core will be employed in Renesas' new RX MCU families that begin rolling out at the end of 2018. The new MCUs are designed to address the real-time performance and enhanced stability required by motor control and industrial applications in next-generation smart factory, smart home and smart infrastructure equipment.
The RXv3 core boosts CPU core architecture performance with up to 5.8 CoreMark/MHz, as measured by EEMBC benchmarks. The core combines a design optimized for power efficiency and a fabrication process producing excellent performance. The new RXv3 CPU core is primarily a CISC (Complex Instruction Set Computer) architecture that offers significant advantages over the RISC (Reduced Instruction Set Computer) architecture in terms of code density. RXv3 utilizes a pipeline to deliver high instructions per cycle (IPC) performance comparable to RISC.

The new RXv3 core builds on the RXv2 architecture with an enhanced pipeline, options for register bank save functions and double precision floating-point unit (FPU) capabilities to achieve high computing performance, along with power and code efficiency.



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This white paper from Mentor addresses several of the pervasive myths within the PCB verification market, such as the need for post-layout PCB verification on high-speed designs. 

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New IDE Version Shrinks Arm MCU Executable Program Sizes
    
After a successful beta period, Segger Microcontroller has added the new Linker and Link-Time Optimization (LTO) to the latest release build of their cross-platform integrated development environments, Embedded Studio for ARM and Embedded Studio for Cortex-M.

The new product versions deliver on the promise of program size reduction, achieving a significant 5-12% reduction over the previous versions on typical applications, and even higher gains compared to conventional GCC tool chains. These savings are the result of the new LTO, combined with Segger's Linker and Run-time library emLib-C. Through LTO, it is possible to optimize the entire application, opening the door for optimization opportunities that are simply not available to the compiler.

The Linker adds features such as compression of initialized data and deduplication, as well as the flexibility of dealing with fragmented memory maps that embedded developers have to cope with. Like all Segger software, it is written from scratch for use in deeply embedded computing systems. The size required by the included runtime library is significantly lower than that of runtime libraries used by most GCC tool chains.